1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and particularly to a method for manufacturing MOS transistors used in DRAMs, logic circuits, etc.
2. Description of the Background Art
FIGS. 47 to 54 are sectional views showing a conventional method for manufacturing CMOS transistors (CMOSFETs). The CMOS transistor manufacturing method will now be described referring to these diagrams.
First, as shown in FIG. 47, element isolation regions 61 are selectively formed in the upper part of a silicon substrate 60. Next, a P well region 83 and an N well region 84 (both of which include a channel region) are formed by ion implantation etc. in the NMOS region 81 and the PMOS region 82 which are isolated by the element isolation regions 61. A silicon oxide film 62 and a polysilicon layer 63 are then sequentially deposited on the entire surface of the silicon substrate 60.
Next, as shown in FIG. 48, resist 64 is formed on the polysilicon layer 63 and patterned by photolithography.
Next, as shown in FIG. 49, the polysilicon layer 63 and the silicon oxide film 62 are etched using the patterned resist 64 as a mask to obtain gate electrodes (interconnections) 65 and gate oxide films 79.
Subsequently, as shown in FIG. 50, resist 66 is formed on the entire surface and patterned so that it remains only in the PMOS region 82, and N-type impurity ions 67 are implanted relatively shallowly from the surface of the silicon substrate 60 by using the patterned resist 66 and the gate electrode 65 in the NMOS region 81 as masks to obtain N-type diffusion regions 68 (68a and 68b).
Next, as shown in FIG. 51, a silicon oxide film is deposited on the entire surface and etched back to form side walls 69 (69a and 69b) of silicon oxide film on the sides of the gate electrodes 65.
Subsequently, as shown in FIG. 52, resist 70 is formed on the entire surface and patterned so that the resist 70 remains only in the NMOS region 81, and P-type impurity ions 71 are implanted relatively deep from the surface of the silicon substrate 60 by using the patterned resist 70 and the gate electrode 65 and side walls 69 in the PMOS region 82 as masks, so as to obtain P-type diffusion regions 72 (72a and 72b). The P-type diffusion regions 72 are formed deeper from the surface of the silicon substrate 60 than the N-type diffusion regions 68.
Next, as shown in FIG. 53, resist 73 is formed all over the surface and patterned so that the resist 73 remains only in the PMOS region 82. N-type impurity ions 74 are then implanted relatively deep from the surface of the silicon substrate 60 by using the patterned resist 73 and the gate electrode 65 and side walls 69 in the NMOS region 81 as masks, thus forming N-type diffusion regions 75 (75a and 75b) which are merged with the previously formed N-type diffusion regions 68 to form main source/drain regions.
The N-type diffusion regions 75 serve as the source/drain regions of the NMOS transistor and the N-type diffusion regions 75 under the side walls 69 serve as extension regions 75ae and 75be which are shallower from the surface of the silicon substrate 60.
Next, as shown in FIG. 54, an interlayer insulating film 76 of silicon oxide film is deposited all over the surface. A thermal process applied in this process causes the N-type diffusion regions 75 and the P-type diffusion regions 72 to further diffuse to form N-type diffusion regions 77 (77a and 77b) and P-type diffusion regions 78 (78a and 78b). Accordingly, the formation depth of the extension regions 77ae and 77be in the N-type diffusion regions 77 is deeper than that of the extension regions 75ae and 75be. Also, the formation depth of the extension regions 77ae and 77be is made deeper than that of the N-type diffusion regions 68 by thermal processes performed between the formation of the N-type diffusion regions 68 and the formation of the interlayer insulating film 76.
The semiconductor device having the CMOS transistors is then completed through existing processes such as interconnecting etc.
Important factors to enhance the driving capability and operating speed of MOSFETs and improve the short-channel characteristic include the reduction of gate dimension (gate length), reduction of source/drain resistance, and formation of shallower PN junctions.
Among these factors, obtaining shallower PN junctions, or forming shallower extension regions, can be achieved by reducing the amount of thermal treatments which are performed after the formation of the extension regions and contribute to the impurity diffusion. However, in the conventional CMOS transistor manufacturing method as shown in FIGS. 47 to 54, thermal processes such as annealing are performed, after the formation of the N-type diffusion regions 68 as extension regions, to form the side walls 69 and to activate the N-type diffusion regions 75 as the main source/drain regions; the thermal processes diffuse the extension regions further deeper, which makes it difficult to form shallower PN junctions.